Google has just given the clearest signal yet that the hyperscaler chip wars are entering a new phase, and it isn’t just about who builds the fastest silicon. It’s about who owns a piece of the company building it.
On 19 August, Marvell Technology disclosed a commercial agreement, signed on 29 July, under which it will design a broad range of custom semiconductors for Google’s Tensor Processing Unit ecosystem: AI inference accelerators, storage controllers, network interface controllers, memory interface controllers and near-memory compute. In exchange, Marvell has issued Google a warrant to buy up to 58.97 million shares at $206.58 each, worth roughly $12.2 billion if fully exercised. Most of that vests only as Google hits purchasing thresholds, one tranche for every $500 million in qualifying revenue, running through fiscal 2033. If every tranche vests, the deal implies as much as $120 billion in custom silicon revenue for Marvell and would make Google the company’s fifth-largest shareholder.
Marvell’s stock jumped more than 10% on the news. Broadcom, Google’s longstanding custom chip partner, fell more than 5%, as markets weighed the arrival of a credible second supplier inside Google’s TPU supply chain.
For an audience building, financing and operating the infrastructure this silicon eventually lands in, the headline number is less interesting than the structure behind it, and what that structure implies for the next few years of capital planning.
Equity-for-commitment is becoming the standard chip deal
This is not an isolated arrangement. It follows Nvidia’s $2 billion strategic investment in Marvell in March, tied to the NVLink Fusion platform, and echoes the shape of AMD’s deal with OpenAI last October, in which OpenAI received the option to buy up to roughly 10% of AMD in exchange for chip purchase commitments. Broadcom, for its part, extended its own long-term Google agreement back in April.
What’s notable is that all three of the major US hyperscalers now run live custom silicon programmes with Marvell: Amazon’s Trainium ASIC work, Microsoft’s Maia programme, and now Google’s TPU-adjacent chips. Marvell CEO Matt Murphy has previously framed the company’s custom silicon strategy as central to its growth.
The pattern suggests that equity stakes, rather than straightforward supply contracts, are becoming the mechanism hyperscalers use to lock in chip capacity while chipmakers use it to lock in demand visibility for multi-year fabrication and R&D commitments. For anyone underwriting or investing in the data centres that will eventually house this silicon, that’s a meaningfully different risk profile than a standard purchase order relationship.
What it means for the infrastructure layer
This is where the story becomes directly relevant to conversations already happening at events like Metro Connect Fall and Datacloud USA this September, where power density, cooling strategy and fast-track construction dominate the agenda but rarely connect back to what’s actually driving those requirements at the chip level.
Custom inference-optimised silicon, memory processing units designed to sit alongside TPUs, and near-memory compute architectures each carry different power and thermal profiles to general-purpose GPU clusters. A facility designed around Nvidia-heavy assumptions doesn’t necessarily flex cleanly to accommodate a mixed TPU-MPU rack, and as Google, Amazon and Microsoft all diversify their silicon suppliers simultaneously, operators need visibility into which architecture is landing where, and when, to plan power and cooling procurement with any confidence.
There’s also a supply chain concentration question worth watching. Marvell now sits inside all three hyperscaler ecosystems, which is good news for Marvell’s revenue diversification but introduces a single point of dependency for the industry more broadly. If Marvell’s design or fabrication capacity becomes a bottleneck, that has ripple effects across three separate hyperscaler build programmes at once, a scenario that deserves more attention in data centre site selection and construction timelines than it currently gets.
The investment and M&A angle
For the investment and legal community converging on Austin, the equity warrant structure itself is worth scrutiny. Tying vendor equity to purchasing milestones through 2033 effectively embeds a long-dated call option on hyperscaler capex discipline into Marvell’s cap table, and by extension into how lenders and ABS structures underwriting fibre and data centre assets should think about compute supply risk as a variable, not a constant.
Vendor concentration, chip architecture diversification, and equity-linked supply agreements are becoming as material to digital infrastructure due diligence as power availability and permitting timelines already are. As the M&A and financing conversations at Metro Connect Fall’s Investment and Finance Summit turn to how capital is being allocated in the AI era, the semiconductor layer underpinning all of that demand deserves a seat at the table alongside the power and construction questions that currently dominate.
Broadcom’s April agreement with Google, still Google’s primary custom chip relationship, runs through 2031, meaning this isn’t a displacement story yet. But with Marvell now embedded across all three hyperscalers and equity-linked deal structures spreading fast, the chip supply layer is arguably the least well understood part of the AI infrastructure build-out right now, and the part most directly shaping what gets built, how it’s cooled, and how it’s financed over the next decade.
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