That refers to a three-dimensional design that stacks and staggers transistors vertically rather than continuing to shrink them horizontally.
Announced today, the new chip packs nearly 100 billion transistors onto an area roughly the size of a fingernail, almost twice the density of IBM’s 2 nm chip introduced in 2021. IBM projects the architecture will deliver up to 50% more performance, or 70% greater energy efficiency, compared with that earlier generation.
The nanostack approach builds on nanosheet technology, the current leading-edge transistor architecture, by adding a third dimension. Rather than fabricating transistors independently across a flat surface, IBM layers them sequentially, allowing different materials to be used within each tier to optimise performance and power independently.
The company has validated the design through functional CMOS inverter operation and demonstrated a 40% improvement in SRAM scaling, a development with direct implications for AI workloads where memory bandwidth is increasingly the binding constraint.
“We’re not just making smaller transistors, we’re reinventing how chips are built,” said Jay Gambetta, director of IBM Research. “This is a meaningful leap forward.”
IBM puts commercial production on a five-year horizon, with data centre deployments expected to follow within a decade. Analysts at TechInsights described the announcement as “transformational.” IBM says the roadmap supports at least a further decade of semiconductor scaling.
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