TSMC's $1.5tn chip forecast signals decade of pressure on AI data centre networks

Kevin Zhang, senior vice president and deputy co-COO at TSMC, delivered the revised outlook at the company’s North America Technology, where he made a point that deserves more attention than it has received: the AI and HPC share of that market alone, 55%, or roughly $825 billion would be larger than the entire global semiconductor market today. Smartphones, which defined chip industry growth for the better part of two decades, are relegated to 20%. Automotive takes 10% and IoT another 10.

This represents a fundamental reordering of what the chip industry exists to serve, and it carries consequences that reach well beyond the fabs in Hsinchu and Phoenix.

What the packaging roadmap actually means

The technology announcements at the symposium attracted significant coverage, most of it focused on process nodes. The A13 node, a direct shrink of A14, targeting 2029 production, and the N2U extension of TSMC’s 2nm platform, expected in 2028, are meaningful steps forward. But for the connectivity and infrastructure sector, the more consequential developments were in packaging.

TSMC is scaling its CoWoS, Chip on Wafer on Substrate, platform at a pace that reflects the extraordinary density requirements of AI compute. The company is currently producing CoWoS at 5.5 times reticle size.

By 2028, it is targeting a 14-reticle configuration capable of integrating approximately ten large compute dies and twenty HBM stacks in a single package. A 40-reticle System-on-Wafer solution follows in 2029.

These are not abstract engineering milestones. As more compute and memory are integrated into a single package, the data flows between those packages and between the servers, racks and facilities that house them, grow proportionally more intense.

Greater integration at the chip level does not reduce interconnect demand; it concentrates and amplifies it, pushing higher bandwidth requirements up the stack into the network. The operators of AI data centres, and the carriers and wholesale providers who connect them, will feel this pressure directly.

TSMC also confirmed that its co-packaged optics technology remains on track for production in 2026. The company has said the technology promises to double power efficiency and cut data centre latency by up to 90%. If that performance holds at scale, it would represent a significant shift in how AI inference and training clusters handle east-west traffic, with implications for the optical transport and interconnect market that are only beginning to be worked through.

Arizona and the geopolitical supply chain

TSMC’s manufacturing expansion in the United States adds another dimension that the wholesale connectivity and carrier community cannot ignore. The company has now committed more than $65 billion to its Arizona buildout, with six wafer fabs, two advanced packaging plants and one research and development centre planned in total. CoWoS and 3D-IC packaging capability at the Arizona site is targeted before 2029.

The strategic logic is well understood: concentrating advanced semiconductor production in Taiwan carries geopolitical risk that governments and large technology customers have spent several years trying to reduce. But the operational consequence of distributed leading-edge manufacturing is a more complex and geographically dispersed AI supply chain, one that requires robust, low-latency connectivity between facilities, between chip designers and their foundry partners, and between the data centres that ultimately deploy the silicon.

For network operators, this is an argument for continued investment in subsea and terrestrial routes connecting North America and Asia-Pacific, and for the kind of high-capacity, low-latency infrastructure that hyperscale AI campuses will demand as production ramps.

The foundry market as a benchmark

Zhang’s projection that the global foundry sector alone could reach $500 billion by 2030 provides a useful benchmark for scale. The foundry market is a subset of total semiconductor revenue — it represents the contract manufacturing piece, not the value of chips sold to end markets. If the foundry segment alone approaches $500 billion, the downstream infrastructure required to support the AI workloads that silicon enables will dwarf that figure.

Data centre construction, power infrastructure, cooling systems, fibre backhaul, subsea capacity, interconnection services, all of these scale with AI compute demand. TSMC’s revised forecast is, in effect, a leading indicator for capital expenditure cycles that will run through the network industry for the rest of the decade.

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